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http://lit.stromquist.com/docs/BLUE%20RIDGE%20TECHNOLOGIES/SPEC%20SHEETS/RK5SpecSheet.pdf 電路佈局驗證(英語:Layout versus schematic,LVS)是一種電子設計自動化(英語:electronic design automation,EDA)工具,其功能為驗證特定積體電路與其原始電路設計之間的差異有無異常。設計規範驗證(英語:design rule check,DRC)可修正並檢驗佈局(layout)是否符合設計規範,但DRC無法保證在佈局完全符合設計規範的情況下,線路依舊維持設計者的預期,而LVS則是這個階段的最適合的解決方案。 the ability to receive or contain storage
Rohan Dutta - Digital Design Engineer - Intel …
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